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UNIVERSITY OF ILLINOIS URBANA-CHAMPAIGN

Research Park

    UIUC Research Park Intern – FPGA Design

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    Posted: 8.17.26

    UIUC Research Park Intern – FPGA Design

    Rivian

    • Student Employment & Internships

    About Rivian

    Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract.

    As a company, we constantly challenge what’s possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations.

    Role Summary
    Internship Term: Fall 2026

    Rivian internships are experiences optimized for student candidates. To be eligible, you must be an undergraduate or graduate student in an accredited program during the internship term with an expected graduation date between December 2026 through May 2028. Rivian’s Internship Program requires active student enrollment. Information regarding your expected degree completion date is collected solely to verify eligibility and determine your availability for future full-time opportunities. Rivian is an equal opportunity employer and does not use graduation dates to determine the age of applicants or as a basis for discriminatory hiring decisions.  

     If you are not pursuing a degree, please see our full time positions on our Rivian careers site. 

     Note that if your university has specific requirements for internship programs, it is your responsibility to fulfill those requirements. 

    We are seeking a motivated FPGA Design Engineering intern to join our Hardware-in-the-Loop (HIL) validation team. In this role, you will help build and maintain cutting-edge HIL testing infrastructure designed to evaluate and validate next-generation autonomous driving systems. You will focus on translating algorithmic camera data processing models into robust FPGA hardware implementations, configuring system-level IPs, and supporting end- to-end hardware-software integration.

    Responsibilities

    • Algorithm-to-RTL Implementation: Translate existing fixed-point mathematical models into optimized, custom camera data processing RTL modules.
    • RTL Development: Write robust custom RTL modules in SystemVerilog, Verilog, or VHDL to manage high-throughput data flows and control logic.
    • IP Integration: Instantiate, configure, and integrate third-party and vendor soft IPs (e.g., memory controllers, high-speed interconnects, standard interfaces) into the top-level design.
    • Simulation & Timing Verification: Set up and run functional simulations, analyze timing reports, perform static timing analysis (STA), and resolve timing violations to ensure design stability.
    • Build & Bitstream Management: Manage the full FPGA build flow (synthesis, place-and-route), generate bitstreams, and handle target FPGA hardware flashing and bring-up in the lab.
    • Cross-Functional Collaboration: Partner closely with system software engineers to ensure the FPGA hardware architecture seamlessly supports software integration, data transfer interfaces, and real-time processing demands.
    • HIL Validation Support: Participate in hardware bring-up, debugging, and continuous integration testing within the autonomous vehicle HIL testing framework. 

    Qualifications

    • Must be currently pursuing a bachelors, masters, or PhD degree at the University of Illinois Urbana Champaign
    • Actively pursuing a degree or one closely related in Electrical Engineering, Computer Engineering, or Computer Science
    • Hands-on experience with SystemVerilog, Verilog, or VHDL through coursework, academic projects, or internships.
    • Solid understanding of digital logic design, finite state machines (FSMs), pipelining concepts, fixed-point arithmetic, and basic digital signal/data processing principles.
    • Familiarity with major FPGA EDA suites (e.g., AMD/Xilinx Vivado, Intel Quartus) and simulation tools (e.g., ModelSim, QuestaSim, Vivado Simulator).
    • Basic understanding of common system buses and interfaces (e.g., AXI4, APB, PCIe, Ethernet, SPI, or UART).
    • Strong analytical and debugging skills with a willingness to work hands-on with hardware testing equipment (logic analyzers, oscilloscopes).

     

    Preferred Qualifications:

    • Exposure to video/image processing pipelines or camera protocols (e.g., MIPI CSI-2 and GMSL).
    • Scripting experience (Python, TCL, or Bash) for automating build flows, simulations, and data analysis.
    • Basic understanding of C/C++ or embedded software development to better interface with software teams.

     

    #LI-HH2

    Pay Disclosure

    The salary range for this role is $25.00-40.00 per hour for Illinois based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs.

     

    We offer a comprehensive package of benefits including but not limited to paid vacation, paid sick leave, and medical insurance benefits. Internship positions are not eligible for retirement benefits.  More information about benefits is available at rivianbenefits.com.

     

    You can apply for this role through careers.rivian.com at UIUC Research Park Intern – FPGA Design in Champaign, Illinois | Rivian(or through internal-careers-rivian.icims.com if you are a current employee). There is no fixed deadline for this application; applications are accepted on an ongoing basis until the role is filled or the opening is no longer needed.